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zeldelra AMD64 (also x86-64 or x64) is a 64-bit microprocessor architecture and corresponding instruction set designed by Advanced Micro Devices. It is a superset of the x86 architecture, which it natively supports. The AMD64 instruction set is currently implemented in AMD's Athlon 64, Athlon 64 FX, Athlon 64 X2, Turion 64, Opteron and later Sempron processors. In an ironic twist of computing history, it has been adopted (under the name EM64T) by Intel—the original creators of the x86 processor line—in its newer Pentium 4, Pentium D, Pentium Extreme Edition, Celeron D, and Xeon processors.

[edit] Features

AMD's x86-64 instruction set (later renamed AMD64) is an extension of Intel's IA-32 (x86-32) architecture. The primary defining characteristic of AMD64 is "64-bitness:" support of 64-bit general purpose registers, 64-bit integer arithmetic and logical operations, and 64-bit virtual addresses. The designers took the opportunity to make other improvements as well. The most significant changes include:

Full support for 64-bit integers: All general-purpose registers (GPRs) are expanded from 32 to 64 bits, and all arithmetic and logical operations, memory-to-register and register-to-memory operations, etc., are now directly supported for 64-bit integers. Pushes and pops on the stack are always in eight-byte strides, and pointers are eight bytes wide.

Additional registers: In addition to increasing the size of the general-purpose registers, their number is increased from 8 in x86-32 to 16. There is therefore less need to save registers, restore registers, and generally manage registers to cope with a shortage of register space, and most arguments to most procedures can be passed in registers rather than on the stack. This should be a significant area of speed improvement once optimized applications appear, especially for software with computationally-intensive deeply-nested loops. This addresses one of the most outstanding deficiencies of x86-32. However, AMD64 still has fewer registers than many common RISC processors which often have 32 registers, as well as the IA-64 architecture which has 128.

Additional XMM registers: Similarly, the number of 128-bit XMM registers (used for Streaming SIMD instructions) is also increased from 8 to 16.

Larger virtual address space: Current processor models implementing the AMD64 architecture can address up to 256 tebibytes of virtual address space (248 bytes). This limit can be raised in future implementations to 16 exbibytes (264 bytes). This is compared to just 4 gibibytes for 32-bit x86.

Larger physical address space: Current implementations of the AMD64 architecture can address up to 1 tebibyte of RAM (240 bytes); the architecture permits extending this to 4 pebibytes (252 bytes) in the future (limited by the page table entry format). In legacy mode, Physical Address Extension (PAE) is supported, as it is on most current 32-bit x86 processors, allowing access to a maximum of 64 gibibytes.

Instruction pointer relative data access: Instructions can now reference data relative to the instruction pointer (RIP register). This makes position independent code, as is often used in shared libraries and code loaded at run time, more efficient.

SSE instructions: The original AMD64 architecture adopted Intel's SSE and SSE2 as core instructions. SSE3 instructions were added in April 2005. SSE2 replaces the x87 instruction set's IEEE 80-bit precision, with the choice of either IEEE 32-bit or 64-bit floating-point math. This provides floating-point operations compatible with many other modern CPUs. The SSE and SSE2 instructions have also been extended to support the eight new XMM registers. SSE and SSE2 are available in 32-bit mode in modern x86 processors; however, if they're used in 32-bit programs, those programs will only work on systems with processors that support them. This is not an issue in 64-bit programs, as all processors that support AMD64 support SSE and SSE2, so using SSE and SSE2 instructions instead of x87 instructions doesn't reduce the set of machines on which the programs will run. Since SSE and SSE2 are generally faster than, and duplicate most of the features of, the traditional x87 instructions, MMX, and 3DNow!, the latter are redundant under AMD64.

No-Execute bit: The “NX” bit (bit 63 of the page table entry) allows the operating system to specify which pages of virtual address space can contain executable code and which cannot. An attempt to execute code from a page tagged "no execute" will result in a memory access violation, similar to an attempt to write to a read-only page. This should make it more difficult for malicious code to take control of the system via "buffer overrun" or "unchecked buffer" attacks. A similar feature has been available on x86 processors since the 80286 as an attribute of segment descriptors, however this works only on an entire segment at a time. Segmented addressing has long been considered an obsolete mode of operation, and all current PC operating systems in effect bypass it, setting all segments to a base address of 0 and a size of 4 GiB. AMD was the first x86-family vendor to support no-execute in linear addressing mode. The feature is also available in legacy mode on AMD64 processors, and recent Intel x86 processors, when PAE is used.

Removal of older features: A number of "system programming" features of the x86 architecture are not used in modern operating systems and are not available on AMD64 in long mode. These include segmented addressing (although the FS and GS segments remain in vestigial form, for compatibility with Windows code), the task state switch mechanism, and Virtual-8086 mode. These features do of course remain fully implemented in "legacy mode," thus permitting these processors to run 32-bit and 16-bit operating systems without modification. If, at some point in the future, 32-bit code using those features is no longer used, support for them might be removed from hardware to streamline processor design and save manufacturing costs. These features could be emulated in the operating system to preserve legacy application compatibility. .